/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/

#ifndef __ETH2_CAN_H__
#define __ETH2_CAN_H__

#include "lwrb/lwrb.h"
#include "VCan_Command.h"
#include "../hscg_flexcan/Hscg_SwFifo.h"
#include "VCan_Types.h"
#include "hscg_firmware.h"
#include "sq_buffer/sq_buffer.h"

// CAN2ETH队列元素
typedef struct CAN_2_ETH_QE {
   uint32 datalen : 7;      //最大数据长度64
   uint32 can_bus_id : 4;   //1722报文需要填can_bus_id字段，代表从哪个can通道进入
   uint32 can_identify : 11; //can报文的identify
   uint32 rtr : 1;          //can RTR位
   uint32 eff : 1;          //can EFF位
   uint32 brs : 1;          //can BRS位
   uint32 fdf : 1;          //can FDF位
   uint32 esi : 1;          //can ESI位
   uint32 rsvd1 : 5;        // Reserved
   uint32 data_ptr;         //数据的位置指针
   uint64 timestamp;        // Timestamp
} CAN_2_ETH_QE;

// ETH2CAN队列元素
typedef struct ETH_2_CAN_QE {
   uint32 datalen : 7;      //最大数据长度64
   uint32 can_bus_id : 4;   //1722报文需要填can_bus_id字段，代表从哪个can通道进入
   uint32 rsvd0 : 11;
   uint32 rtr : 1;          //can RTR位
   uint32 eff : 1;          //can EFF位
   uint32 brs : 1;          //can BRS位
   uint32 fdf : 1;          //can FDF位
   uint32 esi : 1;          //can ESI位
   uint32 rsvd1 : 5;        // Reserved
   uint32 data_ptr;         //数据的位置指针
   uint32 can_identify : 29;      //can报文的identify
   uint32 rsvd2 : 3;
   uint32 timestamp;
} ETH_2_CAN_QE;

// CAN->ETH方向SRAM定义
#define CAN_2_ETH_QUEUE_SRAM_ADDR        0x4874000
#define MAX_CAN_2_ETH_QUEUE_LEN          512
#define CAN_2_ETH_QUEUE_SRAM_ADDR_END    (CAN_2_ETH_QUEUE_SRAM_ADDR + MAX_CAN_2_ETH_QUEUE_LEN * sizeof(CAN_2_ETH_QE))

#define CAN_2_ETH_DATA_SRAM_ADDR         0x4840000
#define CAN_2_ETH_DATA_SRAM_ADDR_END     (CAN_2_ETH_DATA_SRAM_ADDR + MAX_CAN_DATA * MAX_CAN_2_ETH_DATA_LEN)

#define MAX_CAN_DATA                     0x40
#define MAX_CAN_2_ETH_DATA_LEN           512

//ETH->CAN方向SRAM定义
#define ETH_2_CAN_QUEUE_READ_PTR         0x48FF000
#define ETH_2_CAN_QUEUE_WRITE_PTR        0x48FF004
#define ETH_2_CAN_QUEUE_SRAM_ADDR        0X48FE000
#define MAX_ETH_2_CAN_DATA_LEN           256
#define ETH_2_CAN_QUEUE_SRAM_ADDR_END    (ETH_2_CAN_QUEUE_SRAM_ADDR + MAX_ETH_2_CAN_DATA_LEN * sizeof(ETH_2_CAN_QE))

// statistics统计信息保存区域,sizeof(struct STATISTICS)大小为512B
#define STATISTICS_SRAM_ADDR             0x4876000
#ifdef STATISTICS_CODE_TIMESTAMP_ENABLE
#define STATISTICS_CODE_TIMESTAMP_SRAM_ADDR             0x4900000
#define STATISTICS_CODE_TIMESTAMP_SRAM_ADDR_END         (STATISTICS_CODE_TIMESTAMP_SRAM_ADDR + 0x40000)
#endif
#ifdef STATISTICS_PACKET_TIMESTAMP_ENABLE
#define STATISTICS_PACKET_TIMESTAMP_SRAM_ADDR             0x4940000
#define STATISTICS_PACKET_TIMESTAMP_SRAM_ADDR_END         (STATISTICS_PACKET_TIMESTAMP_SRAM_ADDR + 0x40000)
#endif

//VCAN使用的区域（TCM）
//路由表的设计请见方案文档：https://blacksesame.feishu.cn/wiki/IXzyw81OLi03RrkpkpQcwlzSnmg?fromScene=spaceOverview
//路由表1(也叫fast_route_table)
#define VCAN_BASE_ROUTE_TABLE_TCM_ADDR                  0x4848000
#define VCAN_BASE_ROUTE_TABLE_SIZE                      (16*1024)   //16K
#define VCAN_BASE_ROUTE_TABLE_TCM_ADDR_END              (VCAN_BASE_ROUTE_TABLE_TCM_ADDR + VCAN_BASE_ROUTE_TABLE_SIZE)

//路由表2(也叫common_route_table)
#define VCAN_COMMON_ROUTE_TABLE_TCM_ADDR                0x484C000
#define VCAN_COMMON_ROUTE_TABLE_SIZE_EACH_CONTROLLER    (1024)      //每个通道1K,总共16K
#define VCAN_COMMON_ROUTE_TABLE_TOTAL_SIZE              (LLCG_CONFIG_MAXCTRL_COUNT*VCAN_COMMON_ROUTE_TABLE_SIZE_EACH_CONTROLLER) //16k 
#define VCAN_COMMON_ROUTE_TABLE_TCM_ADDR_END            (VCAN_COMMON_ROUTE_TABLE_TCM_ADDR + VCAN_COMMON_ROUTE_TABLE_SIZE)

//CAN TX方向数据暂存区域(包括CAN2CAN ETH2CAN SST2CAN AUTOSAR2CAN)
#define CAN_TX_DATA_BUFFER_ADDR                         0x4850000
#define CAN_TX_DATA_BUFFER_SIZE_EACH_CONTROLLER         2048        //每个通道2K,总共32K
#define CAN_TX_DATA_BUFFER_TOTAL_SIZE                   (LLCG_CONFIG_MAXCTRL_COUNT*CAN_TX_DATA_BUFFER_SIZE_EACH_CONTROLLER)
#define CAN_TX_DATA_BUFFER_ADDR_END                     (CAN_TX_DATA_BUFFER_ADDR+CAN_TX_DATA_BUFFER_TOTAL_SIZE)

//CAN2 X数据暂存（使用sqbuff库管理,包括CAN2ETH CAN2AUTOSAR CAN2SST)
#define CAN2X_DATA_BUFFER_ADDR                          0x4858000
#define CAN2X_DATA_BUFFER_TOTAL_SIZE                    (32*1024)
#define CAN2X_DATA_BUFFER_ADDR_END                      (CAN_TX_DATA_BUFFER_ADDR+CAN_TX_DATA_BUFFER_TOTAL_SIZE)

//CAN2 X共享内存区域
#define CAN2X_SQ_ADDR                                   0x4876200
#define CAN2X_SQ_SIZE                                   sizeof(SQ_Buffer)
#define CAN2X_SQ_ADDR_END                               (CAN2X_SQ_ADDR + CAN2X_SQ_SIZE)

extern volatile uint32* eth_2_can_q_read_ptr;
extern volatile uint32* eth_2_can_q_write_ptr;
void check_module_info(void);
void eth2can_run(void);
void eth2can_init(void);

#endif /* __ETH2_CAN_H__ */
